prevent write/write collision in on-chip True Dual Port Ram

Hello Pete,

The idea of connecting both NIOS to the same Ram is to let them exchange data between each oother. I mean, both of processors needs some data from each other, and each defined data will be saved in a predefined address in the Ram, and Processor A will write to this predefined address, at the same time(or later) Processor B could read or write also to the same address.

My question was if it is really efficient to implement such memory manager in C code? I am talking here in the aspect of timing.

In C code I know how to do it, but if it should be done in HDL, I can not imagine how to do it.

Best Regards