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Zarquin's avatar
Zarquin
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Presentation of the Avalon-MM CV HIP for PCIe?

Dear community, I'm confused about this figure from the ug_c5_pcie_avmm.pdf: What is depicted here? Are these the inputs and outputs of the (1) Avalon-MM CV Hard IP for PCI Express IP core or are ...
Zarquin's avatar
Zarquin
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hello Wincent_C_Intel,

thank you very much for your reply!

Is there a signal among the blue pipe signals that indicates the end or the beginning of a TLP package?

Best Regards

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    The blue pipe signals carry the TLP data before it is serialized.

    It is a 32-bit parallel interface between the PCIe IP Core and PHY

    It is available for simulation only and provides more visibility for debugging.

    Regards,

    Wincent_C_Intel