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Zarquin's avatar
Zarquin
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Presentation of the Avalon-MM CV HIP for PCIe?

Dear community, I'm confused about this figure from the ug_c5_pcie_avmm.pdf: What is depicted here? Are these the inputs and outputs of the (1) Avalon-MM CV Hard IP for PCI Express IP core or are ...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

I wish to follow up with you on this case. Do you still have further inquiries on this issue? I will remain this loop open for 3 days.

If we do not receive any response from you to the previous answer that I have provided.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

Wincent_C_Intel