Presentation of the Avalon-MM CV HIP for PCIe?

Hi,

Thanks for your feedback, I try to answer in detail one by one based on my understanding.

What is depicted here? Are these the inputs and outputs of the (1) Avalon-MM CV Hard IP for PCI Express IP core or are these, as the picture title suggests, only the entrances and exits of the (2) CRA -

• Yes, the block diagram mentions the inputs and output of AVMM IP core of but The optional CRA port for the full-featured IP core allows upstream PCI Express devices and external Avalon-MM masters to access internal control and status registers. Both Endpoint and Root Port applications can use the CRA interface.

according to my understanding, the cra slave signals are only the signals of the upper left corner. Or are these the inputs and outputs to and from the

• Yes, those input and output are from application layer in big picture, but it might also connected with other block diagram as well you may refer the detail of routing using RTL viewer in Quartus

(3) Application Layer as the box labelling suggests - in my opinion, at least the PIPE interface and tx_out and rx_in serial signals and the do not lead to the application layer, (the latter to the pcie lanes)?

• the BLUE arrow means for simulation purposes only. This is a 32-bit parallel interface between the PCIe IP Core and PHY. It carries the TLP data before it is serialized. It is available for simulation only and provides more visibility for debugging.Note: You cannot change the width of the PIPE interface.

Let me know if you need any further clarification or I miss understanding anything.

Regards,

Wincent_C_Intel