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Zarquin's avatar
Zarquin
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Presentation of the Avalon-MM CV HIP for PCIe?

Dear community, I'm confused about this figure from the ug_c5_pcie_avmm.pdf: What is depicted here? Are these the inputs and outputs of the (1) Avalon-MM CV Hard IP for PCI Express IP core or are ...
Zarquin's avatar
Zarquin
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hello Wincent,

thank you for your effort, but it really doesn't help me, because that wasn't my question.

Regards

Zarquin