Possible Bug in IP Compiler for PCI express 128-bit itnterface

Can't say anything about that version, there. I have worked on a block using Avalon ST Stratix IV (Gen2 x8 128 bit) and V (Gen3 x8 256 bit) and the alignment worked as stated in the manual, for both RX and TX, CplD or MWr requests. I did simulate also using a Cyclone IV IP, the highest rate supported by Quartus at the time and did not see any problem.

Just make sure you watch two details that caught us all the time. First the CplD lower address is in bytes and therefore you have to drop the first two bits of the address. The alignment counts on bit 2. The MWr requests are in DW addressing (if you defined the two lower bits as reserved as stated in the spec). Of course, also the MWr matters if it is 64 bit or 32 bit addressing, but the CplD always have 3DW headers so it is like they were always 32 bit addressing.