Point me in the right Direction - PCIe

It is also worth squeezing as much info as possible into the words that are read by PIO.

I did think about making the 'interrupt pending' register (1 bit per interrupt source) be 'read and clear' instead of using a write to clear the bits down. But that causes problem when running a diagnostic program to dump the register area!

Our fpga is directly connected to a PPC on the same card. I carefully worked the software interface between the two parts to minimise the number of separate PCIe transfers - in our case the fpga is always a slave (I got 16M SDRAM put down for buffers, everything else is internal).

I did have to get the ppc to use dma (embedded in the PCIe controller of the ppc we are using - no linux support) in order to get adequate throughput. Since a 128 byte dma transfer (1 PCIe request) doesn't take much longer than a single cycle, the driver just spins waiting for the tranfser to complete (actually they are double bufferred with copies to/from userspace).

For the medium speed IO this was fast enough and doesn't slug the ppc that much (this is part of why we have a ppc).