Honored Contributor
Honored ContributorI have been promised the BFM should return in Q12 (so for now, Im pumping out anything I want to look at in modelsim with 10.1).
There is VHDL support, and the core can be generated fully (with working examples) in either. But afaik, it was all origionally created in verilog, and the VHDL isnt much more than a "port" /auto code-conversion. It works though. I have also raised issues with 1 reference design being supplied with a signaltap file with all the signal references being wrong ( I assume they updated the ref design without updating the ST file - whoops) and subsystem and subsystem vendor IDs not maching those expected by the supplied PC driver (so even though windows thinks its not working, the demo GUI works fine!) luckily, I dont think I will need anything too complicated. I have the attached architecture (see attached image) to implement. With it only being a 16k shared RAM, Im hoping I can just use legacy interrupts and just service mem read/write request, and send back the completions. So - any help appreciated :)
