Honored Contributor
Honored ContributorI'll add my input and hope it doesn't put you off. As a background I've been doing FPGA design for about 15 years now, mostly with Altera devices with Quartus and Modelsim. I don't know the tools intimately but I have a fair idea how to drive them.
Before you start I would certainly read round the PCI interface. You don't have to know anything about the physical layer or the transactions but the configuration, BAR set up etc is useful/ required background. I designed my own PCI slave core so bought the PCI spec (it was $400 odd from memory) but some judicious Googling will probably get you a PDF. I had a design I had done for a client with a Cyclone III on a PCI board I had designed. This used my logic with the Altera PCI master core memory mapped interface. This worked well, DMA to memory, interrupts etc all working nicely. My client wanted the same thing in a PCIe board. I designed a new board with a Cyclone IV intending to use the hard IP with a MM interface. that was the easy bit. This is off the top of my head so a few of the small details might be slightly wrong... As you say when it comes ot the PCIe core the documentation isn't good. There are a few example builds about but there's very little explanation about what's going on if you want to start from scratch with a 'clean' build. The example build in the Wiki for the Cyclone IV with a single lane is (/was) broken. There's a reconfiguration module that has to be included with the PCIe hard core. This drives the transceiver optimisation at power up (amongst other options). In the example Verilog project the signals to and from this to the core aren't declared in the code. I only found out after some googling that undeclared verilog wires are implicitly 1 bit wide so the build fails with a critical error that this module is unconnected. (It works though). This example has many virtual pin, and other unexplained assignments in the qsf. The qsf is ~26kb. The example design in the Quartus installation directory is _very_similar (not broken) to the wiki example but it's not a complete project. This doesn't include any of the virtual pin assignments in the wiki example. From memory the qsf is ~ 1Kb. With the Altera PCI core a script was generated to apply all the necessary constraints. With the PCIe core the same script constrains _1_ clock. There is little/no explanation as to what constraints are required for the hard IP implementation. The multitude of assignments in the Wiki example really muddies the water here. I used Qsys to generate the hard IP core with a MM interface. When the core is generated there are a lot of 'spurious' ports added, these pertain to the PIPE and Test outputs. There's no explanation what to do with them. In the Wiki example above many of these are left unconnected (even inputs). In my VHDL instance I have brought them to the top level and assigned 'Z'. to inputs, leaving outputs 'open'. Also be prepared to be disappointed if you want to simulate in VHDL. From what I understand the support for VHDL simulation has been dropped, although I wonder if that's a side effect of the PCIe BFMs having been dropped. It'll be interesting to see what's included with QII V12.0 I'm sure I have had other problems but as I said this is a quick rant off the top of my head. I am really un-impressed with the quality of the documentation, quality control with the example build etc, it is un-acceptable. I am in the position now where it is all working apart from our interrupts failing after a period but I'm unsure if that's a HW/FPGA or SW/Driver problem yet. Good luck. Nial
