Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThe ST sink 'ready' signal is most likely tied to the FIFO not empty signal inside it so there wouldn't be an easy way to work around it in the IP. So basically when the SGDMA is idle you want the sink port to become blocking correct? If so you might find it easier to hack the modular SGDMA up on the altera wiki to do that. I think it would be just a matter of masking the sink 'ready' signal with (length != 0).