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Altera_Forum
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14 years ago

Pixel shifting with SGDMA in burst mode

Hello All, I am developing a high speed digital video transfer interface between a video DSP and central memory of a PC for a frame grabber card. I use Altera Cyclone IV GX 22 chip with ...
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Altera_Forum
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14 years ago

The ST sink 'ready' signal is most likely tied to the FIFO not empty signal inside it so there wouldn't be an easy way to work around it in the IP. So basically when the SGDMA is idle you want the sink port to become blocking correct? If so you might find it easier to hack the modular SGDMA up on the altera wiki to do that. I think it would be just a matter of masking the sink 'ready' signal with (length != 0).