TonyCosentino
New Contributor
New ContributorPin Delays for Intel Cyclone 10 GX
I need to find out if the Intel Cyclone 10 GX FPGA has a published pin delays to support DDR wiring.
Forum Discussion
sstrell
Super Contributor
Super ContributorWhen you parameterize the EMIF IP, you provide information to the tool to minimize skew based on board simulations. You can choose whether the skew adjustments are performed in the device or that you will be matching delays in your board design. See this online training and the Board tab of the EMIF IP parameter editor for details:
https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1122.html
AminT_Intel
Regular Contributor
Regular ContributorHello Tony,
Is there any update on your end? I will close this case in 3 days if there no update.
Thanks
- AminT_Intel
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
