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CaptainPrice15's avatar
CaptainPrice15
Icon for New Contributor rankNew Contributor
1 year ago

Pin allocation for PCIe HIP gen 2 x1 with Avalon-MM Interface

I wish to use the Intel HIP for cyclone 10GX with a F780 package. I wish to use only 1 lane of PCIe 2.0 with Avalon-MM as interface. The quartus software is allowing me to place the tx pin pair only ...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi，

​

Hope my previous reply clear the doubt of the pin implementation.

I might be miss-out something, please let me know you think I could better clarified/help out.


Regards,

Wincent_Altera​