PICIE hard IP status and statistics

Question

Hi
We are currently using a Hard IP on an Arria10 device , in certain host platforms we get to a point that the LTTSM goes to reconfiguration mode and the driver is disconnected,
We believe that it has something to do with the bus congestion so we want to see statistics of the core (waiting time, errors, number of out packets etc.).
Any suggestions?

rahul_s_intel1 · Answer

May I have the status of LTSSM state.
Please check the reset status also

shmuel_karp · Answer

When we get to the problem we have LTSSM status of
01100: Recovery.Rcvlock

rahul_s_intel1 · Answer

Hi ,
 I feel like it is CDR lock issue.
Can u please check the below iteam. Attaching the FTA for PCIe debugging . The next course of action is given the Excel sheet

a
 Check if LTSSM looping at Recovery.Rcvlock (C )

b
Signaltap rxelecidle0 ,rx_std_signaldetect &amp; rx_is_lockedtodata.  If rxelecidle0 = 0, rx_std_signaldetect = 1 and rx_is_lockedtodata is toggling, it indicates CDR cannot lock. From this test, it can be determined which lane is experiencing CDR loose lock.

c
Check if FPGA Rx receive 1024 TS1 order set sent by far end Tx through protocol analyzer. Alternatively, check if FPGA Rx input is receiving data packet (Rx input is toggling) through oscilloscope.

d
Measure PCIe Refclk is meeting jitter and phase noise specification using oscilloscope and spectrum analyzer

e
If Gen2 using 3.5dB pre-emphasis settings, increase to 6dB to check if CDR able to lock. From this test, it can determined if CDR loose lock is related to incoming signal to RX input having too much ISI or Vid is too small

rahul_s_intel1 · Answer

Excel file

rahul_s_intel1 · Answer

Hi ,
 If you do not have further questions, may I close the case

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PICIE hard IP status and statistics

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a	Check if LTSSM looping at Recovery.Rcvlock (C )
b	Signaltap rxelecidle0 ,rx_std_signaldetect & rx_is_lockedtodata. If rxelecidle0 = 0, rx_std_signaldetect = 1 and rx_is_lockedtodata is toggling, it indicates CDR cannot lock. From this test, it can be determined which lane is experiencing CDR loose lock.
c	Check if FPGA Rx receive 1024 TS1 order set sent by far end Tx through protocol analyzer. Alternatively, check if FPGA Rx input is receiving data packet (Rx input is toggling) through oscilloscope.
d	Measure PCIe Refclk is meeting jitter and phase noise specification using oscilloscope and spectrum analyzer
e	If Gen2 using 3.5dB pre-emphasis settings, increase to 6dB to check if CDR able to lock. From this test, it can determined if CDR loose lock is related to incoming signal to RX input having too much ISI or Vid is too small