New Contributor
New ContributorWhen we get to the problem we have LTSSM status of
01100: Recovery.Rcvlock
Frequent ContributorHi ,
I feel like it is CDR lock issue.
Can u please check the below iteam. Attaching the FTA for PCIe debugging . The next course of action is given the Excel sheet
| a | Check if LTSSM looping at Recovery.Rcvlock (C ) |
| b | Signaltap rxelecidle0 ,rx_std_signaldetect & rx_is_lockedtodata. If rxelecidle0 = 0, rx_std_signaldetect = 1 and rx_is_lockedtodata is toggling, it indicates CDR cannot lock. From this test, it can be determined which lane is experiencing CDR loose lock. |
| c | Check if FPGA Rx receive 1024 TS1 order set sent by far end Tx through protocol analyzer. Alternatively, check if FPGA Rx input is receiving data packet (Rx input is toggling) through oscilloscope. |
| d | Measure PCIe Refclk is meeting jitter and phase noise specification using oscilloscope and spectrum analyzer |
| e | If Gen2 using 3.5dB pre-emphasis settings, increase to 6dB to check if CDR able to lock. From this test, it can determined if CDR loose lock is related to incoming signal to RX input having too much ISI or Vid is too small |
Frequent ContributorExcel file
Frequent ContributorHi ,
If you do not have further questions, may I close the case
