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nome
Occasional Contributor
Occasional ContributorPFL not use
Hello
During FPGA configuration from MAX II with parallel flash by Intel P33 series
if I don't want to use PFL IP on CPLD. I am using my own HDL codes for fpga configuration
start pages de...
NurAiman_M_Intel
Super Contributor
Super ContributorWe do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
