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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

PFL not use

Hello During FPGA configuration from MAX II with parallel flash by Intel P33 series if I don't want to use PFL IP on CPLD. I am using my own HDL codes for fpga configuration start pages de...
NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Thank you for contacting Intel community.


The option bit is meant for the PFL IP. If you used your own codes, when generate from .sof to .pof, Quartus will generate the bit for you. Can you clarify why need to know the option bits?


Regards,

Aiman