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Altera_Forum
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16 years ago

PFL implementation and CFI interface on STRATIX4 design

I am using a the same design used in the reference board of stratix4 GX for the configuration interface of the FPGA. The configuration mechanism is implemented in a MAXII device (2210F256) and a flas...
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Altera_Forum
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16 years ago

Hi Philippe,

Thanks for your response! I don't have a watchdog timer in my design, so it looks like we have different problems - I will keep looking.

Best Regards,

Jody