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Altera_Forum
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16 years ago

PFL implementation and CFI interface on STRATIX4 design

I am using a the same design used in the reference board of stratix4 GX for the configuration interface of the FPGA. The configuration mechanism is implemented in a MAXII device (2210F256) and a flas...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes I found it,

We used the same MAXII design supplied by ALTERA with one of SIV GX design reference board. A watchdog function is intantiated in this design and this last was appropriates for a SIV230GX but not for SIV530GX.

To analyse this issue I have compliled my 2 projects (230 & 530) to obtain rbf files. For the 230 devive the rbf flie size is about 10 MB and for 530 devive the rbf flie size is about 20 MB. Then I have deducted that the number of DCLK cycle should have been proportionnal ... it wasn't the case. By instrumenting the PFL signals I have identifed that the configuration cycle of SIV530GX was interupted by another function in the design ... it was the watchdog. I have modified the watchdog counter value to solve this issue.

Best regards,

Philippe