Contributor
ContributorHi @YuanLi_S_Intel ,
Thanks for your replies so far. Please comment here too (urgent to know please).
>> First of all, if you are using RBF file, you need to write your own controller to do programming and configuration as PFL IP is not supporting RBF file.
What file formats does the PFL IP support other than .pof that we can identify its contents ?
or how can we decode the contents of a .pof file?
Does it just contain the OPTION_bits data followed by the Page data info and no other headers involved?
If it does great. But need confirmation.
eg Page 1
.map file generated for the corresponding .pof file for Page1 was :
--------------------------------------------------------
BLOCK START ADDRESS END ADDRESS
Page_1 0x00440000 0x0085241B
OPTION BITS 0x00000000 0x00000080
Notes:
- Data checksum for this conversion is 0xB8A3B1AF
- All the addresses in this file are byte addresses
----------------------------------------------------------------
Regards,
Kevin
ContributorWill appreciate a reply to my previous msg.
Our latest updates :
Chunks of bytes will be send via I2C to the CPLD via FPGA (FPGA is just a middle man, pass through i2c data to CPLD).
So configuration data will be coming from FPGA to CPLD now. Data manipulation will be done in the CPLD. CPLD contains one PFL (see next paragraph) & will update the flash Device. I will need to supply data to the combined loader_config_pfl with some manipulation of course. Could this data be .pof format (knowing its structure?). Then the writing data to the flash will be held automatically by the combined loader_config_pfl itself (which I am trying to test right now, not remotely to get that to work first)
Wrt another ticket I created, we are trying to combine now 'flash programming' + 'FPGA configuration' using one PFL. Having other issues here at the moment not knowing how to control the handshaking signals pfl_flash_access_granted & pfl_flash_access_request to achieve successful flash programming & FPGA configuration. Your reply to this matter will be appreciated too. In this instance we are not sending any data across via I2C.
With this test I am doing now (having issues with the 2 handshaking signals how to properly control), we are:
1) Programming/configuring the CPLD with the combined loader_config.pof
2) Then after power cycle, autodetecting the flash device
3) Then we program/Configure the flash with the application page data .pof
=> We expect to see successful Flash programming & FPGA configuration at the end of this test
------
Could we have byte of data that can be converted to JTAG kind of data for the loader_config_pfl to understand? or can you propose other ways to achieve this?
ie need to be able to extract the data (eg .pof) & supply it to the loader (this will be implemented in VHDL).
What is the best way of achieving this ?
It is very important to know what the .pof structure format looks like otherwise will not now what data will be sending across to the loader and how the loader will receive it and understand it?
Regards,
Kevin
