Hi,
Used <auto> mode and managed to generate the .pof file successfully.
Page_0 start address: 0x00020000 end address: 0x0043241B
Page_1 start address: 0x00440000 end address: 0x0085241B
Page_2 start address: 0x00860000 end address: 0x00C7241B
Option bits start address: 0x0000000 end address: 0x00000080 <- .pof version
Start addresses were generated automatically on a 128KB boundary (actually 2^17 = 131,072)
Thanks for this.
1) But the .map file generated stated that all addresses in the .map file are byte addresses. Does it mean each address location contains a byte of data ?
---
2) However, still need someone to explain wrt Parallel Flash Loader Intel FPGA IP User Guide pg17 :
"Page Start Address, End Address, and Page-Valid Bit Stored as Option Bits" Fig12 diagram ? It states that it is using flash byte addressing mode
It states that Bits 0 to 12 for the page start address are set to zero and are not stored as option bits.
Is that for a 28bit address (27:0) : Address(12:0) are always set to '0'?
I am confused from the fig12 byte addressing mode shown. The Bit7....Bit1 at eg 0x002000 address does this correspond to the data and bit 0 of the start address of each page is 'Page-Valid' bit?
If Bit7....Bit0 corresponds to the data, what about address 0x002002 shows only 7 bits of data ie Bit7...Bit1 ?
or are those bits representing the address bits?
Very confusing..
3) Our system uses flash_addr(25:0) & flash_data(15:0). How will we address our PFL correctly ?