Periodic Pulses Pattern
Hello,
I'm a new Verilog programmer and still rely on examples to write code.
I didn't find any example of what I need.
I need to generate two pulses periodicaly like this following schema:
...
Forum Discussion
FvM
Super Contributor
Super ContributorHello,
apart from the point that outputs have no purpose in a testbench, the problem in your original code are of different kind.
Assignment must take place outside the initial statement.
`timescale 1us/1ns
module Pulses(clk, pulse1, pulse2);
output reg clk, pulse1, pulse2;
reg c, p1, p2;
initial
begin
c = 0;
p1 = 0;
p2 = 0;
repeat(1000) //1000 cycles repeated
begin
#0 c = 1;
#1 c = 0;
#2 p1 = 1;
#1 p2 = 1;
#1 p1 = 0;
#2 p2 = 0;
#1 ;
end
end
assign clk = c;
assign pulse1 = p1;
assign pulse2 = p2;
endmodule
