Periodic Pulses Pattern
Hello,
I'm a new Verilog programmer and still rely on examples to write code.
I didn't find any example of what I need.
I need to generate two pulses periodicaly like this following schema:
...
Forum Discussion
Nurina
Regular Contributor
Regular ContributorHello,
That doesn't look like a testbench. How are you simulating this? Are you using ModelSim/QuestaSim?
I tried using QuestaSim and managed to get the output you want.
First of all, a testbench shouldn't have any ports declaration -> module Pulses(clk, pulse1, pulse2);
It should be empty like so -> module Pulses ();
And I don't think you can use assign in testbench.
Please refer to the verilog files I'm attaching. periodic_pulses.v is the top verilog file in your Quartus project and periodic_pulses_tb.v is the testbench.
Follow the steps here to compile and run simulation, it should be the same for Quartus Lite:
QuestaSim: https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html
ModelSim: https://www.intel.com/content/www/us/en/docs/programmable/683248/18-0/simulation-quick-start.html
Regards,
Nurina
p/s: If any answer from the Intel Support is helpful, please feel free to provide rating with 4/5 survey on the support provided.
