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JET60200's avatar
JET60200
Icon for Contributor rankContributor
5 years ago

PCtoFPGA AVMM DMA data-transfer cann't complete in time randomly using A10 PCIe AVMM IP

hello experts, we are using A10 HIP AVMM IP design as a PCIe device to pug inside X86 XEON SERVER to work with. In Linux driver, we program FPGA AVMM DMA Engine to transfer bulk-data between...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY