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JET60200's avatar
JET60200
Icon for Contributor rankContributor
4 years ago

PCtoFPGA AVMM DMA data-transfer cann't complete in time randomly using A10 PCIe AVMM IP

hello experts, we are using A10 HIP AVMM IP design as a PCIe device to pug inside X86 XEON SERVER to work with. In Linux driver, we program FPGA AVMM DMA Engine to transfer bulk-data between...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Could you share the STP for the below signals and the .ip file? Please use translational for storage qualifier setting.


Txs

dma_rd_master

dma_wr_master

wr_dts_slave

rd_dts_slave

wr_dcm_master

rd_dcm_master

Rxm_BAR*

tx_out0[<n>-1:0]

rx_in0[<n>-1:0]

hip_reconfig_clk

hip_reconfig_rst_n

hip_reconfig_address[9:0]

hip_reconfig_read

hip_reconfig_readdata[15:0]

hip_reconfig_write

hip_reconfig_writedata[15:0]

hip_reconfig_byte_en[1:0]

ser_shift_load

interface_sel

npor

nreset_status

pin_perst

refclk

RdDmaWrite_o

RdDmaAddress_o[63:0]

RdDmaWriteData[<w>-1:0]

RdDmaBurstCount_o[<n> -1:0]

RdDmaByteEnable_o[ <w>-1:0]

RdDmaWaitRequest_i

WrDmaRead_o

WrDmaAddress_o[63:0]

WrDmaReadData_i[<w >-1:0]

WrDmaBurstCount_o[<n>-1:0]

WrDmaWaitRequest_i

WrDmaReadDataValid_i

cfg_par_err

derr_cor_ext_rcv

derr_cor_ext_rpl

derr_rpl

dlup

dlup_exit

ev128ns

ev1us

hotrst_exit

ins_status[3:0]

ko_cpl_spc_data[11:0]

ko_cpl_spc_header[7:0]

l2_exit

lane_act[3:0]

ltssmstate[4:0]

rx_par_err

tx_par_err[1:0]

currentspeed[1:0]

Cra*


Thanks

Best regards,

KhaiY