Forum Discussion
Aflop
Occasional Contributor
Occasional ContributorPCIe with DMA Memory Sizing
Background : I am currently using the Arria 10 GX Devkit in preparation for a similar custom board. I have adapted the PCIe Avalon-MM DMA example which Intel provides and come up with a custom desig...
RongY_altera
Contributor
ContributorIf you want multiple Bars to access one on-chip mem, please try AVMM Pipeline Bridge IP. You can define your address width there.
Regards,
Rong
AflopOccasional Contributor
Occasional ContributorThis is not the accepted solution. I already have multiple BARs. I never said I wanted them to access one on-chip mem. Maybe it is the accepted solution for YOUR problem but it is not what I asked.
I have multiple BARs access multiple on-chip Mem and it is working fine other than the lspci command does not reflect the correct size. I have moved on to other problems of more importance now. When I have time to investigate this again I will.
