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I sent an email to you.
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I've responded to it.
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This board is not sold separately, but is part of a larger system, so it is integrated with a known (tested) motherboard in all situations.
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Great. Then your job now is to document these timing requirements, and the requirements for the motherboard. If you do not do this now, some poor soul (perhaps yourself) will have to figure out why things are not working with "the new motherboards" some time in the future.
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FPGA reconfiguration has to be finished for the PCIe hardIP to respond to config read requests from the motherboard?
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FPGA reconfiguration and link training has to be complete - the details are in the timing figure I referred you to earlier.
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Yes, I have M29EW flash device (micron), and it supports the page buffer read mode (with 25ns read access time), but seems like the PFL doesnt have that option. I only have a spansion page mode access (in advanced read mode) listed, which gave me a slight improvement in read latency, but it still takes more than 500ms to configure the FPGA.
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Ignore what PFL gives you. Do the math. What is the fastest you should be able to configure the FPGA? If the best you can do is close to this number, then there is no reason to change the implementation.
However, even if you find you can make it faster, you do not need to (since your motherboard is ok with the current timing). Just document that the design could be improved, and show how. Later if this product needs to be revised, these types of changes can be made.
Cheers,
Dave
Honored Contributor
