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I checked the CPLD, we are using a 50MHz clock and Flash access time (from where the data is fetched by CPLD) is about 70ns, and due to that each byte is taking about 100ns to be sent to the FPGA during configuration. The configuration data for our device is about 6MBytes and that explains why CPLD takes about 600ms to finish the reconfiguration. Yes, I still need to check why there is some extra time taken on a cold boot, but I may not still be able reconfigure the FPGA within 100ms, or not even 500ms.
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Ok, so this is a design "feature" then. This complicates the use of this board, since it will work in some motherboards, but not others.
The board designer's responsibility is to perform a timing analysis (like the one in the doc I linked to) and as shown in this doc:
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf For example, see the timing diagram on p30 where 16-bit flash reads are used to program an FPGA in FPP mode. The flash read access timing is what limits the design. Using page-mode flash helps. Review your design. Perhaps the board has page mode flash, and you're not using that feature. That might allow you to speed things up slightly.
Cheers,
Dave
Honored Contributor
