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This "fix" is causing you other problems, so really you need to fix this problem first.
Send me an email to my forum name and I'll forward an email discussion that I had on this topic.
This is not good. You need to determine all of your power on timing delay sources, eg., look at your on-board power-supplies, their ramp times, etc. Your board may be violating the power-on-requirements of the FPGA, i.e., hiding even more issues.
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Thanks. I am going to look at why there is that significant delay during cold boot than on a warm boot.
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Generating another reset is not going to help. What you are not looking at in these traces is the PCIe bus activity. Your PCIe end-point will miss the traffic on the bus that configures it. If its working in this motherboard, then its just luck. The next motherboard you plug it into, it may not work.
The "solution" is to;
1) Configure the FPGA at power-on "as fast as possible", ideally within 100ms, but if you cannot achieve that, then faster than the deassertion of PCIe reset.
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I checked the CPLD, we are using a 50MHz clock and Flash access time(from where the data is fetched by CPLD) is about 70ns, and due to that each byte is taking about 100ns to be sent to the FPGA during configuration. The configuration data for our device is about 6MBytes and that explains why CPLD takes about 600ms to finish the reconfiguration. Yes, I still need to check why there is some extra time taken on a cold boot, but I may not still be able reconfigure the FPGA within 100ms, or not even 500ms.
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2) Do not reconfigure when PCIe reset asserts. There is no reason to.
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Yeah, I agree. I am going to make the change, Thanks!
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The FPGA just needs to treat the PCIe reset as a reset source. You don't have to reset all logic within the FPGA if you do not want to, eg., you can have a "last reset reason" register that sets a power-on bit at power on, and a PCIe reset bit when PCIe reset occurs (of course if your FPGA configures faster than PCIe reset deasserts, then you'll only ever see the PCIe reset bit set).
Cheers,
Dave
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