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When the CPLD first powers on, it should program the FPGA. There is no need to program the FPGA when PERST# asserts.
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You are right, I had it that way before, but faced some issues with binary update at site when the host PC just does a warm boot after a system update. So now I just put it to update every time there is a PCIe reset.
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Yeah, you can use hot-plug under Linux. I'm not sure about Windows.
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I would like to understand how to do that(in linux), Can you please point me to any docs? or give some more info, Thanks! We have PC platform, but I may get some idea.
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If you are using a CPLD to program the FPGA, then you should have a pretty good idea as to how long programming will take. So how long is that?
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I had to check it.. Its taking about 600ms, and since there is an internal delay or something on a powerup, it takes more than a sec (1100ms) after powerup before the FPGA is programmed and ready.
So definitely I am missing the pcie reset (in both cases, PC Cold Boot/Warm boot) I attached the waveforms as well. So, I am going to generate a reset after the PCIe reset and the reconfiguration.
PC after Cold Boot (there is a mistake in signal name, pink is fpga config done)
https://www.alteraforum.com/forum/attachment.php?attachmentid=7070 PC After Warm boot
https://www.alteraforum.com/forum/attachment.php?attachmentid=7071 PC After Warm Boot - Zoomed to show the PERST# since its only a 5ms.
https://www.alteraforum.com/forum/attachment.php?attachmentid=7072
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