--- Quote Start ---
Its quite possible that is the case, and it would probably be acceptable. Its worth poking around in your hardware to get a sense of what is going on at the system level, and then write your testbenches to match that and several other power-up sequences to see if your design behaves correctly.
Cheers,
Dave
--- Quote End ---
Ok so, I got some more data. Seems like after cold boot of the host PC, PCIe reset is asserted for almost ~500ms (see the pic, signal captured). C1(yellow) is the pcie reset and c2 (pink) is the Vcc.
https://www.alteraforum.com/forum/attachment.php?attachmentid=7064 But when I restart the PC, the reset is asserted only for a ~5ms, I am not sure if there is another reset coming after this, but I doubt it. See the pic below
https://www.alteraforum.com/forum/attachment.php?attachmentid=7065 So I think my signaltap in the earlier post shows that the pci reset occured long before the FPGA configuration finished and thats the reason I am not seeing reset being asserted in the waveform. That also means that I am not really getting a proper reset to my FPGA logic (except for the PCIe hard IP block) since all my logic resets are connected to the pcie reset (except for the altgx_reconfig block for which I generated a reset internally).
Honored Contributor
