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Your SignalTap II trace still does not look correct. Your trace shows pcie_rstn high, i.e., deasserted. Offset cancellation should have completed long before reset deasserts, i.e., I would expect to see pcie_rstn low in your traces.
Cheers,
Dave
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Let me see if I understand this correctly. I think the sequence of events is,
1. Powerup of FPGA (PCIe reset is not yet asserted)
2. FPGA Config done
3. altgx_reconfig block gets the reset and goes busy (as in my signaltap) and starts the transciever calibration.
4. altgx_reconfig busy gets deasserted. ready for PCIe handshke with root complex.
5. All these steps up until now shouldnt take more than 100ms. Now the PCIe_rst_n is asserted. And the PCIe hard IP resets and ready for transfer
6. PCIe enumeration... blah blah blah
7. PCIe pkt transfers goes on.
So pcie reset gets asserted after the 100ms time after powerup, my signaltap show the activity just after the fpga config done where pcie reset should be deasserted and will be asserted later on. Am I Correct? Or were you asking why I dont have the pcie_rstn low in my signaltap towards the end of it? I only have only captured 8k samples after powerup(160us)
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