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For the purpose of Transceiver offset cancelation I am using the external alt_gx_reconfig. I have been using a PLL output to feed this clock and using the pll_locked as the reset generator. Like this,
altgx_reconfig altgx_0_reconfig (
.offset_cancellation_reset(~pll_locked), // pll locked
.reconfig_clk (pll_clk_50), // clock from PLL
.reconfig_fromgxb (reconfig_0_fromgxb),
.busy (busy),
.reconfig_togxb (reconfig_togxb)
);
This works perfectly.
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But it is wrong. You should not control the reset signal with a signal that is not deglitched, eg., see Altera's KB example
http://www.altera.com/support/kdb/solutions/rd12172009_309.html and the SignalTap II traces in the PDF associated with this thread:
http://www.alteraforum.com/forum/showthread.php?t=35678 --- Quote Start ---
But I need to free up this PLL and use for another purpose and I am thinking of using a clock coming directly from the pin. And I am not quite sure what to do with the reset
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You could tie it to an on-board power-on reset source.
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Now I am thinking the pcie reset could be connected to the altgx_reconfig. Like this,
altgx_reconfig altgx_0_reconfig ( .offset_cancellation_reset (~pcie_rstn), // PCIe reset
.reconfig_clk (clkin_50), // clock coming from a x'tal
.reconfig_fromgxb (reconfig_0_fromgxb),
.busy (busy),
.reconfig_togxb (reconfig_togxb)
);
But that did not work either. PCI express is not responding.
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That is because the PCIe core needs to start link training as soon as reset deasserts, eg., see p5 of this doc for the requirements.
http://www.ovro.caltech.edu/~dwh/wbsddc/ts4_power.pdf You need to tie the reset to something that deasserts once the FPGA is configured, eg., a reset supervisor input, or an internally generated signal that asserts and then deasserts at power-on.
Cheers,
Dave
Honored Contributor
