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For example how to write data to FPGA2’s onchip memory
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Linux's lspci from the host CPU will tell you the PCIe address of the BAR region that you have mapped the on-chip RAM to. (PCITree can be used under Windows).
Lets say it is 0x1234_5678_0000_0000 on one of the boards.
If you have created a design based on the Qsys PCIe bridge, then the TXS slave interface can generate PCIe transactions. The second board can write to the onchip memory of the other board by issuing a write to the TXS slave. However, the TXS slave can only 'see' a 1MB region of PCIe addresses at any one time, so before issuing the write, the CRA register that sets the most significant bits of the PCIe address needs to be configured with 0x1234_5678_0000_0000, and then your write to the TXS slave will have those address MSBs inserted into the 64-bit address issued on the PCIe bus.
Cheers,
Dave
Honored Contributor
