Altera_Forum
Honored Contributor
Honored ContributorPCIe standalone design
Hello,
I'm trying to use the PCIe IP on my DK-START-4CGX15N board. I don't want to use the chaining DMA example as a starting point. So I instantiated the PCIe _plus variant in a VHDL top design and tried to setup the minimal input signal to get the PCIe link up and the board enumerated by the BIOS.... This is my instance:-----------------------------------------------------------
-- Constant drivers --
-----------------------------------------------------------
test_in(39 downto 0) <= (others => '0');
-----------------------------------------------------------
-- Component instantation --
-----------------------------------------------------------
THE_PCIe : pcie_megawiz_ip_plus
port map ( app_int_sts => '0', -- Controls legacy interrupts
app_msi_num => "00000", -- Application MSI offset number
app_msi_req => '0', -- Application MSI request
app_msi_tc => "000", -- Application MSI traffic class
cpl_err => "0000000", -- Completion error
cpl_pending => '0', -- Completion pending
lmi_addr => (others=> '0'), -- Local Management Interface
lmi_din => (others=> '0'), -- Local Management Interface
lmi_rden => '0', -- Local Management Interface
lmi_wren => '0', -- Local Management Interface
local_rstn => LOCAL_RSTN_EXT, -- Board reset
pcie_rstn => PCIE_RSTN, -- PCIe reset
pclk_in => '0', -- Simulation only (7-11)
pex_msi_num => (others=> '0'), -- Power management MSI number
phystatus_ext => '0', -- PIPE interface phystatus signal
pipe_mode => '0', -- "setting it to 0 selects the 1-bit interface"
pld_clk => core_clk_out, -- (7-2)
pm_auxpwr => '0', -- This signal can be tied to 0 because the L2 power state is not supported
pm_data => (others=> '0'), -- Power Management Data
pm_event => '0', -- Power Management Event
pme_to_cr => '0', -- Power management turn off control register
reconfig_clk => '0', -- "otherwise, when unused, the reconfig_clk signal should tied low"
refclk => REFCLK, -- PCIe clock
rx_in0 => RX_IN0, -- PCIe RX line
rx_st_mask0 => '0', -- Application asserts this signal to tell the IP core to stop sending non-posted requests
rx_st_ready0 => '1', -- Indicates that The application is ready to accept data
rxdata0_ext => (others=> '0'), -- Pipe interface Rx
rxdatak0_ext => '0', -- Pipe interface lane 0 RX data K-character flags
rxelecidle0_ext => '0', -- Pipe interface lane 0 RX electrical idle indication
rxstatus0_ext => (others=> '0'), -- Pipe interface lane 0 RX status flags
rxvalid0_ext => '0', -- Pipe interface lane 0 RX valid indication
test_in => test_in, -- Test in
tx_st_data0 => (others=> '0'), -- Avalon-ST TX Interface
tx_st_eop0 => '0', -- Avalon-ST TX Interface
tx_st_err0 => '0', -- Avalon-ST TX Interface
tx_st_sop0 => '0', -- Avalon-ST TX Interface
tx_st_valid0 => '0', -- Avalon-ST TX Interface
app_clk => open, -- Application clock
app_int_ack => open, -- This signal is the acknowledge for app_int_sts
app_msi_ack => open, -- Application MSI acknowledge
app_rstn => open, -- Application reset
clk250_out => open, -- Simulation only
clk500_out => open, -- Simulation only
core_clk_out => core_clk_out, -- -> pld_clk
lane_act => open, -- Delayed version of test_out on ×4/ ×1 IP core interface
lmi_ack => open, -- Local Management Interface
lmi_dout => open, -- Local Management Interface
ltssm => open, -- Link Training and Status State Machine
pme_to_sr => open, -- Power management turn off status register
powerdown_ext => open, -- PIPE interface powerdown signal
rate_ext => open, -- Simulation only
rc_pll_locked => open, -- Indicates that the SERDES receiver PLL is in locked mode with the reference clock
rx_st_bardec0 => open, -- The decoded BAR bits for the TLP
rx_st_be0 => open, -- These are the byte enables corresponding to the transaction layer's rx_be
rx_st_data0 => open, -- Avalon-ST Rx data
rx_st_eop0 => open, -- Avalon-ST Rx
rx_st_err0 => open, -- Avalon-ST Rx
rx_st_sop0 => open, -- Avalon-ST Rx
rx_st_valid0 => open, -- Avalon-ST Rx
rxpolarity0_ext => open, -- This signal instructs the PHY layer to do a polarity inversion on the 8B10B receiver decoding block
srstn => open, -- ??
test_out => test_out_icm, -- Provide run-time control and monitoring of the internal state of the IP cores
tl_cfg_add => open, -- Configuration Space Signals, Address of the register that has been updated
tl_cfg_ctl => open, -- Configuration Space Signals, The tl_cfg_ctl signal is multiplexed and contains the contents of the configuration space registers
tl_cfg_ctl_wr => open, -- Configuration Space Signals, Write signal
tl_cfg_sts => open, -- Configuration Space Signals, Configuration status bits
tl_cfg_sts_wr => open, -- Configuration Space Signals, Write signal
tx_cred0 => open, -- Transmit credit
tx_fifo_empty0 => open, -- Indicates that the adapter TX FIFO is empty
tx_out0 => TX_OUT0, -- PCIe TX
tx_st_ready0 => open, -- Avalon-ST TX Ready
txcompl0_ext => open, -- Pipe interface, This signal forces the running disparity to negative in compliance mode
txdata0_ext => open, -- Pipe interface
txdatak0_ext => open, -- Pipe interface
txdetectrx_ext => open, -- Pipe interface
txelecidle0_ext => open); -- Pipe interface
