New Contributor
Regular ContributorHi,
Are you using any design example provided in the IP catalog ?
Or that is a custom design ?
If you are using AVST design, you may refer to
it got explain about the reset signal.
If you would like to use the hard reset pin, I would say the nCONFIG pin is the most accurate pin for you. It is a dedicated configuration control input pin where pulling this pin low during user mode causes the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level initiates reconfiguration.
Regards,
Wincent_Intel
