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sambkr's avatar
sambkr
Icon for New Contributor rankNew Contributor
3 years ago

PCie SRNS, separate perstn

Dear Support, I plan to use a PCie switch board to connect a x16 pcie lane inside a PC to 4 FPGA (4 lanes pcie) cyclone 10 GX boards. FPGA boards will be endpoints. The Pcie switch board use mini...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Are you using any design example provided in the IP catalog ?

Or that is a custom design ?


If you are using AVST design, you may refer to

https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/reset-status-and-link-training-signals-reset.html

it got explain about the reset signal.


If you would like to use the hard reset pin, I would say the nCONFIG pin is the most accurate pin for you. It is a dedicated configuration control input pin where pulling this pin low during user mode causes the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level initiates reconfiguration.


Regards,

Wincent_Intel