Forum Discussion

agula's avatar
agula
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

PCIe SR-IOV Arria 10 Configuration Space

Hi All, Is the configuration space handled completely by the IP, or does the memory for the configuration space exist in your application logic memory. For example, is it in the user-space bar log...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

Let me try to answer one by one:


If you set the VF msi-x table size to 2. Does this mean you have two distinct interrupts that can be generated? -> Yes

Does this also mean that every other VF also has this msi-x table of size 2 as well? -> Yes


You can see the table is actually assigned to a BAR that you set in the GUI. And you have to define the table by yourself. The table that mentions here is in Figure 32. Format of MSI-X Table.


I also need more clarification on where the msi-x table and pba table actually reside. For example, if I set BIR to be 0 for VFs. Where does this table actually reside? Is it in the user-application on-chip memory of the VF bar0 at address offset 0? Then to generate an interrupt for VF 1 go to that memory location read the addresses and set the request and set the PBA to the appropriate value?

è If I understand your questions correctly, then the answer is yes for all. It is depending on what component you connect the MSI-X BAR. Most of the user connects it to an on-chip memory that contains the MSI-X table. For details, you may see Figure 31. MSI-X Interrupt Components. Items 1-5.