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LAH20's avatar
LAH20
Icon for New Contributor rankNew Contributor
5 years ago

PCIe RAS DES Features Enabling

Hello , I would like to know how to enable the Synopsys RAS DES Features of the R-tile Hard IP for the Agilex FPGA and also how to access these registers. I have gone through the ug20316.pdf docume...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Since we have communicated internally and there is no other questions, this thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY