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LAH20's avatar
LAH20
Icon for New Contributor rankNew Contributor
5 years ago

PCIe RAS DES Features Enabling

Hello , I would like to know how to enable the Synopsys RAS DES Features of the R-tile Hard IP for the Agilex FPGA and also how to access these registers. I have gone through the ug20316.pdf docume...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


This information is not available as R-tile document is not yet officially released.


Thanks

Best regards,

KhaiY