Forum Discussion
New ContributorPCIe P-Tile Flow Control
Hi Team,
In the PCIe P-Tile TX flow control, user guide says "internally generated TLPs also consume FC credits" Page 72. My questions are
1.How does the user application know how muche credits consumed internally?
2.What will be the impact of this internal unit consumtion on the TDM tx_cdts_limit_o interface, should we expect a decrease in credits, or advertized credits remains same?
3. Can the PCIe IP manage this internal credits consumption or the user application should account this as well while calculating the available credits?
4.In the case of RX flow control, instead of the number of credits, flow control is defined in terms of Number of TLPs. Any examples for this conversion while calculating available credits?
Hi Anat,
On P-tile IP, there is no handling required by user application when credit is consumed due to internally generated TLP. Just that the credit return to user is slower.
This means that HIP decrements new FC_update credits values before to pass them to the user application as TX credit limit when HIP has consumed internal credits.
In that sense user application will have less credits that once sent by PCIe link partner agent in FC_update DLLP.
For example, the RP send FC_update PD=20 and HIP had consumed 4 credits then user application will received PD=16 (TX credit limit signal) where previous TX credit limit value was PD=16 or less.
Does this acceptably answer your question?
Regards,
Wincent
20 Replies
anatThanks. Please close
Wincent_AlteraRegular Contributor
Hi,
I’m glad that your question has been addressed, I now transition this thread to community support. If you have new question, please login to “https://supporttickets.intel.com/s/?language=en_US’, view details of ddesire request, and post a feed/response within net 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on follow-up questions.
Regards,
Wincent_Altera
