Forum Discussion
New ContributorPCIe P-Tile Flow Control
Hi Anat,
On P-tile IP, there is no handling required by user application when credit is consumed due to internally generated TLP. Just that the credit return to user is slower.
This means that HIP decrements new FC_update credits values before to pass them to the user application as TX credit limit when HIP has consumed internal credits.
In that sense user application will have less credits that once sent by PCIe link partner agent in FC_update DLLP.
For example, the RP send FC_update PD=20 and HIP had consumed 4 credits then user application will received PD=16 (TX credit limit signal) where previous TX credit limit value was PD=16 or less.
Does this acceptably answer your question?
Regards,
Wincent
New ContributorAny updates?
Regular ContributorHi ,
I still checking with our design team, it might take sometime.
I will raise this ticket level as top priority, hope can get the feedback soon.
Sorry for keep you waiting.
Regards,
Wincent_Altera
- Wincent_Altera
Hi Anat,
Sorry for keep you waiting.
If for R-tile , there is features where user can sends a value of zero on the rx_buffer_limit_i during CPL timeslot.
BUT, for P-tile those features is not available.But, CPL credit advertised to the link partner by P tile during flow control initialization is infinite if refer to the user guide
value passed by the rx_buffer_limit* interface signal will not affect the value of credit advertised by the HIP to the link partner, the Hip will only initialize credit to the link partner according to the value in the screenshot above, and periodically advertise the credit to the link partner in accordance with the TLP received.
Hope that clarified.
Regards,
Wincent_Altera
