PCIe P-Tile Flow Control

Hi Anat,

On P-tile IP, there is no handling required by user application when credit is consumed due to internally generated TLP. Just that the credit return to user is slower.

This means that HIP decrements new FC_update credits values before to pass them to the user application as TX credit limit when HIP has consumed internal credits.

In that sense user application will have less credits that once sent by PCIe link partner agent in FC_update DLLP.

For example, the RP send FC_update PD=20 and HIP had consumed 4 credits then user application will received PD=16 (TX credit limit signal) where previous TX credit limit value was PD=16 or less.

Does this acceptably answer your question?

Regards,

Wincent