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Altera_Forum
Honored Contributor
10 years agoPCIe protocol implemetation requires a rootport and a endpoint, normally a CPU will acts as rootport, while the FPGA at another end will acts as endpoint.
A software driver at host side may also required to perform the data transfer. PCIe gen1 is 2.5Gbps, Gen2 is 5.0Gbps. For Serial Rapid IO, it supports 1x and 4x serial PHY, speed is either 1.25, 2.5, 3.125, and 5.0 Gbps. In your case, it seems like using Rapid IO is more appropriate compare to PCIe. See attached Rapid IO system diagram.