Forum Discussion

KRow's avatar
KRow
Icon for New Contributor rankNew Contributor
2 years ago

PCIe on Cyclone 10 gx dev kit

I bought the cyclone 10 gx dev kit to learn how to implement PCIe. I do not have large amounts of data to move. Less the 1Gbs, so Gen 2 or Gen 2 is plenty. I have tried the examples for this board...
Pcie
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @KRow,


Yes, these design examples initiate the read/write DMA from the host side. Unfortunately, we do not have design examples where the read/write DMA is initiated from the FPGA side.


May I ask what specific latency you are measuring?

We do not have the information on the internal latency of the PCIe Hard IP. The achievable latency will depend on the specific implementation of the PCIe interface.


Thanks.

Best Regards,

Ven