PCIe MSI Interrupt

To enable MSI interrupts, ensure the CRA port is enabled, host side needs to set the MSI enable bit and Interrupt Disable bit.

1. Set MSI Enable of MSI Control register, this bit is mapped to bit[16] of offset 0x50 in configuration space register.

2. Set Interrupt Disable bit[10] of Command register at configuration space offset register 0x4 to disable legacy interrupt.

3. Set bit[1] (Memory space) and bit[2] (Bus Master) of Command Register at configuration space offset register 0x4 to enable the ability to

generate MSI message.

Once users trigger the rxm_irq, the PCIe core will generates the interrupt message.