Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

PCIE link -up status

Hi , I am migrating an old design i had using a soft PCIE core to cyclone 4's hard IP. I had a 'link-up' status signal which I used to drive an LED whenever the link became active. Is there an equiva...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Sorry about the 10g link up answer - wrong post.

I do have an PCIe Qsys block in our Stratix IV device. From Qsys, I instantiated an "IP_Compiler for PCI Express" (altera_pcie_hard_ip) component. This component provides a "pcie_rstn" output. We use this output as a link up status. We started with Beta Qsys software and now are using 11.0sp1. I mention this because your PICe ports are slightly different than what I have. I am not sure if it is because we started from Beta software or because you using a different Qsys component