PCIE link -up status

pcie_hard_ip_0_fixedclk_clk : in std_logic := '0'; -- pcie_hard_ip_0_fixedclk.clk

pcie_hard_ip_0_pipe_ext_pipe_mode : in std_logic := '0'; -- pcie_hard_ip_0_pipe_ext.pipe_mode

pcie_hard_ip_0_pipe_ext_phystatus_ext : in std_logic := '0'; -- .phystatus_ext

pcie_hard_ip_0_pipe_ext_pll_powerdown : in std_logic := '0'; -- .pll_powerdown

pcie_hard_ip_0_pipe_ext_gxb_powerdown : in std_logic := '0'; -- .gxb_powerdown

pcie_hard_ip_0_pipe_ext_rate_ext : out std_logic; -- .rate_ext

pcie_hard_ip_0_pipe_ext_powerdown_ext : out std_logic_vector(1 downto 0); -- .powerdown_ext

pcie_hard_ip_0_pipe_ext_txdetectrx_ext : out std_logic; -- .txdetectrx_ext

pcie_hard_ip_0_pipe_ext_rxelecidle0_ext : in std_logic := '0'; -- .rxelecidle0_ext

pcie_hard_ip_0_pipe_ext_rxdata0_ext : in std_logic_vector(7 downto 0) := (others => '0'); -- .rxdata0_ext

pcie_hard_ip_0_pipe_ext_rxstatus0_ext : in std_logic_vector(2 downto 0) := (others => '0'); -- .rxstatus0_ext

pcie_hard_ip_0_pipe_ext_rxvalid0_ext : in std_logic := '0'; -- .rxvalid0_ext

pcie_hard_ip_0_pipe_ext_rxdatak0_ext : in std_logic := '0'; -- .rxdatak0_ext

pcie_hard_ip_0_pipe_ext_txdata0_ext : out std_logic_vector(7 downto 0); -- .txdata0_ext

pcie_hard_ip_0_pipe_ext_txdatak0_ext : out std_logic; -- .txdatak0_ext

pcie_hard_ip_0_pipe_ext_rxpolarity0_ext : out std_logic; -- .rxpolarity0_ext

pcie_hard_ip_0_pipe_ext_txcompl0_ext : out std_logic; -- .txcompl0_ext

pcie_hard_ip_0_pipe_ext_txelecidle0_ext : out std_logic; -- .txelecidle0_ext

pcie_hard_ip_0_cal_blk_clk_clk : in std_logic := '0'; -- pcie_hard_ip_0_cal_blk_clk.clk

pcie_hard_ip_0_reconfig_togxb_data : in std_logic_vector(3 downto 0) := (others => '0'); -- pcie_hard_ip_0_reconfig_togxb.data

pcie_hard_ip_0_reconfig_busy_busy_altgxb_reconfig : in std_logic := '0'; -- pcie_hard_ip_0_reconfig_busy.busy_altgxb_reconfig

pcie_hard_ip_0_pcie_rstn_export : in std_logic := '0'; -- pcie_hard_ip_0_pcie_rstn.export

pcie_hard_ip_0_test_out_test_out : out std_logic_vector(63 downto 0); -- pcie_hard_ip_0_test_out.test_out

pcie_hard_ip_0_rx_in_rx_datain_0 : in std_logic := '0'; -- pcie_hard_ip_0_rx_in.rx_datain_0

pcie_hard_ip_0_reconfig_fromgxb_0_data : out std_logic_vector(4 downto 0); -- pcie_hard_ip_0_reconfig_fromgxb_0.data

pcie_hard_ip_0_reconfig_gxbclk_clk : in std_logic := '0'; -- pcie_hard_ip_0_reconfig_gxbclk.clk

pcie_hard_ip_0_tx_out_tx_dataout_0 : out std_logic; -- pcie_hard_ip_0_tx_out.tx_dataout_0

pcie_hard_ip_0_clocks_sim_clk250_export : out std_logic; -- pcie_hard_ip_0_clocks_sim.clk250_export

pcie_hard_ip_0_clocks_sim_clk500_export : out std_logic; -- .clk500_export

pcie_hard_ip_0_clocks_sim_clk125_export : out std_logic; -- .clk125_export

pcie_hard_ip_0_test_in_test_in : in std_logic_vector(39 downto 0) := (others => '0'); -- pcie_hard_ip_0_test_in.test_in

pcie_hard_ip_0_refclk_export : in std_logic := '0' --

this is the top level for the system i generated in QSYS (+plus some other signals from my custom components)

none of these is the "k_fault_status_xgmii_rx" do i need to change some settings in order for this signal to come up? My system consist of a 1 lane PCIE hard IP, DMA and a custom memory-like module.