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New Contributor

5 years ago

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PCIe IP generate support

Hi, I use Stratix10, quartus pro 20.3, I want to generate IP PHY of PCIe, It is important to me that at gen1 the clock rate will be 250MHz with 8bits data. at IP Compiler for PCI Express datas...

Deshi_Intel
5 years ago
HI Moti,

I presume you are using PCIe Gen 1 preset in NativePHY IP.

By default, it will be 10 bits with 125MHz.

You can disable the Tx serializer and Rx de-serializer setting then it will become 8 bits with 250MHz.

Refer to the attached pic in my previous post.

Thanks.

Regards,
dlim

Deshi_Intel

Regular Contributor

5 years ago

HI Moti,

I presume you are using PCIe Gen 1 preset in NativePHY IP.

By default, it will be 10 bits with 125MHz.

You can disable the Tx serializer and Rx de-serializer setting then it will become 8 bits with 250MHz.

Refer to the attached pic in my previous post.

Thanks.

Regards,

dlim

Moti
New Contributor
4 years ago
Hi dlim,

Further to the question on the page

I saw at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf

Table 99. PIPE Gen3 32 bit PCS Clock Rates p.172

that I can choose, gen 1 will work with clock of 62.5MHz , How can I choose this clock rate and use it for pipe clk ?

Thanks,

Moti

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