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Moti's avatar
Moti
Icon for New Contributor rankNew Contributor
4 years ago
Solved

PCIe IP generate support

Hi, I use Stratix10, quartus pro 20.3, I want to generate IP PHY of PCIe, It is important to me that at gen1 the clock rate will be 250MHz with 8bits data. at IP Compiler for PCI Express datas...
  • Deshi_Intel's avatar
    Deshi_Intel
    4 years ago

    HI Moti,


    I presume you are using PCIe Gen 1 preset in NativePHY IP.


    By default, it will be 10 bits with 125MHz.


    You can disable the Tx serializer and Rx de-serializer setting then it will become 8 bits with 250MHz.


    Refer to the attached pic in my previous post.


    Thanks.


    Regards,

    dlim


Moti's avatar
Moti
Icon for New Contributor rankNew Contributor
4 years ago

Hi,

I do want to use the NativePhy IP with the PCIe PIPE interface, and for that I need in Gen 1 that work at clock rate of 250MHz with 8bits data.

at the Data sheet that you referred to at Table 103 I can see that this IP support 125MHz with 16bits or 250MHz with 8bits (that what I need)

But I did not find at the Mega Wizard any option that can I control this, also when I implement that IP I received data of 16bits at 125MHz.

So how can I change/control that to be 250MHz with 8bits ?

Thanks

Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Refer to the steps in attached pic