Forum Discussion
New ContributorPCIe IP generate support
HI Moti,
I presume you are using PCIe Gen 1 preset in NativePHY IP.
By default, it will be 10 bits with 125MHz.
You can disable the Tx serializer and Rx de-serializer setting then it will become 8 bits with 250MHz.
Refer to the attached pic in my previous post.
Thanks.
Regards,
dlim
Regular ContributorHI Moti,
Thanks for the clarification.
First of all, the datasheet/doc link that you shared was 2014 old Altera doc that's definitely not applicable to newer Stratix 10 FPGA.
For the list of supported PCIe IP in Stratix 10 FPGA, pls use below link instead
- https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html
- Goto the left panel and click on "2. user guides and reference designs"
- Scroll down until you see supported PCIe user guide doc for Stratix 10 FPGA. Check out the link to see which PCIe IP suit your applicable needs
- If you scroll until the end then you will find explanation and doc link to NativePHY IP that stated it only support PCIe PIPE mode only, not full PCIe functionality
I presume you want to use complete PCIe IP and not NativePHY IP with PCIe PIPE mode only, right ?
Thanks.
Regards,
dlim
New ContributorHi,
I do want to use the NativePhy IP with the PCIe PIPE interface, and for that I need in Gen 1 that work at clock rate of 250MHz with 8bits data.
at the Data sheet that you referred to at Table 103 I can see that this IP support 125MHz with 16bits or 250MHz with 8bits (that what I need)
But I did not find at the Mega Wizard any option that can I control this, also when I implement that IP I received data of 16bits at 125MHz.
So how can I change/control that to be 250MHz with 8bits ?
Thanks
- Deshi_Intel
Refer to the steps in attached pic
