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Moti's avatar
Moti
Icon for New Contributor rankNew Contributor
4 years ago
Solved

PCIe IP generate support

Hi, I use Stratix10, quartus pro 20.3, I want to generate IP PHY of PCIe, It is important to me that at gen1 the clock rate will be 250MHz with 8bits data. at IP Compiler for PCI Express datas...
  • Deshi_Intel's avatar
    Deshi_Intel
    4 years ago

    HI Moti,


    I presume you are using PCIe Gen 1 preset in NativePHY IP.


    By default, it will be 10 bits with 125MHz.


    You can disable the Tx serializer and Rx de-serializer setting then it will become 8 bits with 250MHz.


    Refer to the attached pic in my previous post.


    Thanks.


    Regards,

    dlim


Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

HI Moti,


We have few PCIe IP solution.


Can you help to clarify which IP and which datasheet doc that you are referring to ?

  • First of all, can you let me know which datasheet doc that you are looking at that clarify support for PCIe Gen 1 with 250MHz ? Can you share with me the doc link and its chapter section/page number ?
  • After that, pls clarify which FPGA IP that you initiated to generate PCIe ? Let me know the exact FPGA IP name. For instance, NativePHY IP or some Avalon MM/ST PCIe or DMA IP and etc...


Thanks.


Regards,

dlim